1. Field of the Invention
The present invention relates to an apparatus of data sensing in semiconductor memory, and more particularly to a method of high speed sensing and circuit restoring in DRAM design.
2. Description of the Relative Art
As shown in FIG. 1A, the conventional DRAM array is mainly comprised of a memory cell MC, which commonly includes a selection transistor T and a storage capacitor C, wherein the gate of the selection transistor T is controlled by a wordline WL. When the wordline WL is selected and results in the ON condition of the selection transistor, charges stored in the storage capacitor C are sent to the bit line BL and sensing amplifier SA. After the comparison of the sensing amplifier SA, the logic output of the memory cell MC is determined and sent to the I/O data line to be read.
As mentioned above, the storage capacitor C discharges during the read of the memory cell MC; thus, the data isn't stored in the memory cell. Therefore, it is necessary for the sensing amplifier SA to restore the charges in the memory cell MC before completing the data reading.
Furthermore, as a semiconductor memory device is highly integrated to reduce the size of the memory cell, there is inevitably a tendency of reduction in parasitic capacitance Cb of the memory capacitor. Various improvements have been made to obtain sufficient difference in input potentials for a sense amplifier SA.
In the U.S. Pat. No. 4,351,034, a shared sense amplifier is disclosed, wherein a memory cell array is divided into two blocks and the sense amplifier is disposed and shared between the two blocks. During the sensing operation, only the columns in one block are connected to the sense amplifier. The columns of the other block are subsequently connected to the sense amplifier after the sensing operation.
With the above-described arrangement, since the number of memory cells connected to one bit line can be reduced, parasitic capacitance of the bit line associated with the memory cells can be reduced. That is, the potential on the bit line varies in proportion to a ratio Cs/Cb of the memory cell capacitance Cs to the bit line capacitance. So that even if the same amount of signal charges are transferred onto the bit line, potential changes on the bit line can be almost twice that in a non-divided cell array.
However, in this construction, the bit line still causes time delays during the sensing of the data in the memory cell because of the large numbers of memory cells, and results in the slow access time of the DRAM cell.